Programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs), can be used in a variety of applications. PLDs offer the advantage of being reprogrammable and are typically reprogrammed in the field (e.g., while remaining on circuit boards in operational environments).
However, a drawback associated with conventional PLDs is their inability to provide desired logic states (i.e., output signal values) on input/output pins while being programmed with new configuration data (i.e., reconfigured). For example, in applications where a PLD does not provide onboard non-volatile memory, it is generally necessary to load new configuration data from an external source into the onboard configuration memory of the PLD. Unfortunately, conventional PLDs typically cannot provide predictable behavior on their output pins while simultaneously loading new configuration data into onboard volatile memory.
More specifically, a conventional PLD may be in a sleep state during reconfiguration, wherein input/output pins are disabled (e.g., non-responsive to input signals while providing indeterminate output signals). Such behavior is generally unacceptable, especially in applications where the PLD is in a critical path or is used to control critical functions. Conventional PLDs can also exhibit glitches in the output signals provided on the output pins during programming and immediately after programming. Such glitches are also unacceptable in critical applications. As a result, there is a need for improved programming and configuration techniques for PLDs.